1. Field of the Invention
The present invention relates to a method of fabricating a complementary metal oxide semiconductor (CMOS) transistor and a CMOS transistor fabricated by the method, and more particularly, to a method of fabricating a CMOS transistor, by which the characteristics of both first and second conductivity type MOS transistors are improved, while simplifying the fabrication process by using a fewer number of masks, and a CMOS transistor fabricated according to the method.
2. Description of the Related Art
As semiconductor devices continue to operate at faster operation speeds and continue to become more highly integrated, various methods for fabricating semiconductor devices with improved characteristics using existing fabrication technology have been proposed to overcome the challenges associated with ever-smaller features. In particular, there has been extensive study in the field of improving electron or hole mobility using a strain effect in a channel portion of a semiconductor device so as to embody a high performance semiconductor device, as disclosed by J. Welser et al. in “Strain Dependence of the Performance Enhancement in Strained-Si n-MOSFETs,” IEDM Tech. Dig. 1994, p 373 and by K. Rim et al. in “Enhance Hole Mobilities in Surface-Channel Strained-Si p-MOSFETs,” IEDM Tech. Dig. 1995, p. 517.
In a typical method for increasing electron or hole mobility as described above, a strained layer is used. If a semiconductor material such as Si or C is implanted into a source/drain region, a tensile stress is created in an X-direction, and thus a tensile-strained layer is formed in a channel region. For this reason, effective mass in the channel region is reduced and electron mobility is increased in turn. On the other hand, if a semiconductor material such as Ge is implanted into the source/drain region, a compressive stress is created in the X-direction so that a compressive-strained layer is formed in the channel region. For this reason, effective mass in the channel region is increased and hole mobility is increased in turn.
In one method of providing a tensile stress or a compressive stress in a channel region portion, materials having different lattice constants are provided in the source/drain region. Such a method is referred to as a heterogeneous epitaxial growth method and there are various methods used to accomplish such growth.
For example, a lattice constant of Si is 5.43 Å and Ge has the same diamond structure as Si and a lattice constant of 5.66 Å which is larger than that of Si. Further, SiGe has the same diamond structure as Si and a lattice constant larger than that of Si and smaller than that of Ge according to the concentration ratio of Ge contained in the Si. For this reason, in a case of growing Si on an upper part of a Sil-xGex layer using the heterogeneous epitaxial growth method, a phenomenon in which a lattice of Si is increased and a lattice of SiGe is reduced is generated so as to identify the lattice of Si with the lattice of SiGe. A method of increasing electron or hole mobility using such a phenomenon has been widely used.
Further, examples of the method of increasing electron or hole mobility include a method of using a strain effect along the entire surface of a substrate and a method of using a local strain effect in a particular portion of a device.
A method of utilizing a local strain effect is disclosed in U.S. Pat. No. 6,605,498 issued on Aug. 12, 2003. The above patent discloses that a lower part of a gate electrode is recessed and then the recessed region is filled with SiGe as a channel material in a case of a p-channel MOS (PMOS) transistor or filled with SiC as a channel material in a case of an N-channel MOS (NMOS) transistor using a selective epitaxial growth method. In the case of utilizing the local strain effect, since Si and SiGe or SiC have different lattice constants, a compressive stress is created in a channel portion of Si in a case of the PMOS transistor and a tensile stress is created in a case of the NMOS transistor. This increases electron or hole mobility in each of the channel portions, thereby making it possible to improve the characteristics of the resulting semiconductor device.
However, in the aforementioned method, it is impossible to fill the recessed region with the channel material after recessing the lower parts of the gate electrodes of the NMOS transistor and the PMOS transistor at the same time. The reason is that the strains required for each of the channel portions for improving the characteristic of the semiconductor device are reversed. For this reason, in the above patent, after recessing only the lower parts of the gate electrodes of the PMOS transistor, a SiGe layer is formed within the recessed region using the selective epitaxial growth method. At this time, a separate mask process is required for preventing the lower parts of the gate electrodes of the NMOS transistor from being recessed.